Parallel sparse LU decomposition using FPGA with an efficient cache architecture
Published in In the proceedings of 2017 IEEE 12th International Conference on ASIC (ASICON), 2017
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Recommended citation: Xiang Ge, Hengliang Zhu, Fan Yang, Lingli Wang, Xuan Zeng, "Parallel sparse LU decomposition using FPGA with an efficient cache architecture." In the proceedings of 2017 IEEE 12th International Conference on ASIC (ASICON), 2017.